Matching tPHYRDLs and disabling Gear Down Mode on Ryzen 7000

I wanted to share my current settings in case anybody else has been struggling with matching tPHYRDLs between sticks and/or disabling Gear Down Mode.

To match tPHYRDLs, I had to first of all bring my VDDQ/VDDIO voltage up to 1.4v (RAM kit stock). I previously had them a 1.1v (Raphael architecture minimum). VDD is at 1.43v (up from 1.4v stock) to get CL-28. I also raised VDDP to 1.106v up from 0.8 (Raphael architecture minimum).

To disable Gear Down Mode, I had to loosen 3(4) timings by 1 tick…

tRCDWR
tRCDRD
tWTRL
tRDRDSCL

tRCD read and write are a single timing on my Asrock x670E PG Lightning and I can't change them individually even under SPD Timings with hex values.

I also raised my tRAS to 126 and set my tRC as low as it would stably go based on buildzoid's latest video on the subject.

I verified stability with 3 hours of TestMem5 Extreme, 3 hours of Prime95 Large FFT's, 3 hours of y-cruncher VT3, and 6 hours of karhu.

Hope this helps someone dial in their own settings!