Voltages are currently :
Vddio 1.37
Vdd/vddq 1.42
Vpp 1.8
Vsoc 1.25
Vddg cdd/iod 1.050
Vdd misc 1.1
Vddp 1.1
Fabric is 2167 and is running 6200mt in uclk=memclk mode.
Aida seems stable after an hour of mem+cache and ycruncher vt3 passes 16 2 min iterations with bit rates cycling between 1.52-1.53×1010 bits/sec. I will do more indepth stability testing later but for now I'm trying to push the limits.
I was wondering if it's possible to get to 26 TCL but everytime I try my PC will boot with the JEDEC defaults. Is it folly to try to get the timings even tighter?
Any pointers on what I should try to focus on lowering or things to loosen if I were to try to reach TCL 26 would be much appreciated!
1 Comment
Your RFC isn’t evenly divisible by 16, rollback to 384. Other that that seems spot on, maybe SCL’s can go lower, but I’m not sure.