In continuation of my previous help post, I would like to share my tweaking experience and results with you here.
A big thanks to
DZCreeper
who helped me to figure out tough things easier and shared resources.
And
buildzoid
And his video https://youtu.be/iux-P7qGe-o
And all who were in the discussion.
My rigs are:
- Motherboard: ROG STRIX X870-A
- Processor: AMD Ryzen 7 9800X3D
- RAM: G.SKILL DDR5 (2x16GB) 7200MT/s CL34-45-45-115 1.40V
- SSD_0: SAMSUNG 990 PRO 1TB
- SSD_1: Transcend 220S 512GB
- GPU: Asus TUF GeForce RTX 4070TS 16 GB
And my timings are:
Primary Timings
– Tcl—————30
– Trcd Wr———–37
– Trcd Rd———–37
– Trp—————32
– Tras————–40
Secondary Timings
– Trc—————72
– Twr—————48
– Refresh Interval–50000
– Trfc1————-416
– Trfc2————-Auto
– Trfcsb————Auto
– Trtp————–12
– TrrdL————-8
– TrrdS————-4
– Tfaw————–20
– TwtrL————-14
– TwtrS————-4
– TrdrdScl———-4
– TrdrdSc———–1
– TrdrdSd———–Auto
– Trdrddd———–Auto
– TwrwrScl———-4
– TwrwrSc———–1
– TwrwrSd———–Auto
– TwrwrDd———–Auto
– Twrrd————-4
– Trdwr————-16
DRAM Signal Control
– UCLK DIV1 MODE—-UCLK=MEMCLK
2 Comments
Would this make your 1% lows better than 7200 mts would?
Highly doubt trrds 4 trrdl 8 tfaw 20 twtrl 14 is faster than, trrds 8 trrdl 12 tfaw 32 twtrl 14.
trcdwr to like 20-14
trp min is tcl+4
tras 49 (57) trcdrd+trtp(+8)
trc 83(91) tras+trp
trdwr 15 (12+wrpre, you can read that out with zentimings dev or asus memtweak)
Twrrd 1
Also run TM5 13.1 1usmus 25 cycles and ddr5&x3d/absolut/extreme for like 2h.
Also with 6200 fclk should not be lower than 3:2 (fclk:uclk) sync, or if higher fclk atleast +100 above 3:2 sync.
trdrdSc, trdrdSd, trdrddd, twrwrSc, twrwrSd, twrwrDd are only used on DR ram.
Nitro settings 1-2-0? Zentimings -> system info
You could also turn igpu = disabled and set bank swap mode = swap apu
Data scramble = disabled
Tsme = disabled
Svm = disabled (disables virtualization)