So I got this set of 4 8gb Sticks recently and tried Ram Oc basically the first time. Any thoughts on the timings and maybe some room for improvements?
Voltage is still at 1.35V Dimm, 1.25 SA. Tried to achieve a higher frequency or better primaries but apart from tRas there was absolutely nothing working with a voltage of up to 1.45V. That´s probably due to it being 4 sticks or rather the die itself?
Got my subtimings pretty good I think, however with reasonably low voltage. tRRD_L will boot at 4 but BSOD immediately, tRDRD and tWRWR at 6 won´t boot but barely. I think I could maybe get those 3 timings tighter with a higher voltage but I´m not sure if thats reliable with the Hynix C-Die, any thoughts on this? Thanks in advance for your feedback!
intelalways
You could try – tRAS – 28 / tREFI – 65535 / tRDRD_dd – 6 / tWRRD_dd – 5 / tWRRD_sg – 26 & tWRRD_dg – 22 (Set tWTR, tWTR_L & tWTR_S to Auto) / Lower RTL’s manually or by enabling Round Trip Latency (You may need to increase tRDWR_sg, tRDWR_dg & tRDWR_dd) / *_dr – 0 / TRDPRE – 6 / OREF_RI – 32 / TXP – 4 / PPD – 0 / DLLBwEn – 4
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So I got this set of 4 8gb Sticks recently and tried Ram Oc basically the first time. Any thoughts on the timings and maybe some room for improvements?
Voltage is still at 1.35V Dimm, 1.25 SA. Tried to achieve a higher frequency or better primaries but apart from tRas there was absolutely nothing working with a voltage of up to 1.45V. That´s probably due to it being 4 sticks or rather the die itself?
Got my subtimings pretty good I think, however with reasonably low voltage. tRRD_L will boot at 4 but BSOD immediately, tRDRD and tWRWR at 6 won´t boot but barely. I think I could maybe get those 3 timings tighter with a higher voltage but I´m not sure if thats reliable with the Hynix C-Die, any thoughts on this? Thanks in advance for your feedback!
You could try – tRAS – 28 / tREFI – 65535 / tRDRD_dd – 6 / tWRRD_dd – 5 / tWRRD_sg – 26 & tWRRD_dg – 22 (Set tWTR, tWTR_L & tWTR_S to Auto) / Lower RTL’s manually or by enabling Round Trip Latency (You may need to increase tRDWR_sg, tRDWR_dg & tRDWR_dd) / *_dr – 0 / TRDPRE – 6 / OREF_RI – 32 / TXP – 4 / PPD – 0 / DLLBwEn – 4