Got my 3200mhz CL14 DDR4 kit running 3733mhz CL15 with GDM off and CR1T. I've never been able to get PHYRDLs to both train at 26 unless I stayed at 3600mhz even. Anytime I broke from 3600mhz it would go out of sync. DIMM A2 at 26 and DIMM B2 at 28. Finally got them both running at 26. I can get some of the timings tighter like CL, RDWR, RP can all go down to 14, RCDRD won't go down from 15. RAS can go down to 22, RC can go down to 36. WTRL can go to 8, RTP can go to 5, WR to 10, RDWR to 8 if CL and CWL are at 14, and SCLs can go down to 2. If I lower the primaries to their tightest timings (CL14), it breaks the PHYRDL sync and runs 26/28. From my understanding, the primaries don't matter all that much because modern computers use RAM in a way that tends to avoid those timings, using different banks and rows as much as possible unless it absolutely has to use the same banks and rows. So, most of the time the secondaries are being the limiting factor. IDK I think that's what buildzoid's video was saying but I could be wrong. Loosening the secondaries to what they're set to currently gained performance over running them at absolute tightest setting. For example, SCLs can go down to 2 and are 8hrs Anta Absolut stable, but I get better performance when running them at 3. Now I'm just waiting for the day that I have to upgrade to DDR5 and learn all this stuff over again lol.