Included two aida pictures, the first was with 1.0v vsoc which performed decent though setting vsoc to 1.15v seems to produce better latency and write speeds. Unsure what to do with tRAS, keep it at 126 or would y'all suggest something lower and follow the tRP+tRAS=tRC rule? I could maybe try for 5/5 SCL's again but last i remember that caused 00 error boot code.. maybe aim for 7/7? tRDWR/tWRRD also seems comfortable at 16/4 any lower and 00 errors again.
I've tried cl32 but that just caused instant TM5 errors and will likely require way more VDD/VDDQ than what im currently running at cl34. Also at 8000 i think this prefers FCLK to be synced with UCLK, desyncing results in better memory scores in aida but drops performance in gaming.. which is what im aiming to improve upon. Also to note having SVM(hypervisor) disabled resulted in worse performance within CS2 but did help lower latency a very small amount, so i keep it enabled
tPHYRDL's are synced 37/37 if you were wondering